1. Field of the Invention
Embodiments of the invention relate to semiconductor device fabrication, and in particular, to methods for reducing gate line deformation and for reducing gate line widths in semiconductor devices.
2. Background Technology
Current semiconductor manufacturing uses a variety of techniques to achieve sub-100 nm gate line widths.
One technique involves the use of amorphous carbon as a hardmask material for patterning polysilicon to form gate lines. FIG. 1 shows a structure used in the formation of a gate line using this technique. The structure includes a semiconductor substrate 2 having shallow trench isolations 4 that bound an area in which a MOSFET is to be formed. A gate insulating layer 6 such as silicon oxide and a gate conductive layer 8 such as doped polysilicon are formed over the substrate and will be patterned to form a gate line and gate insulator of the MOSFET. Formed over the gate conductive layer 8 is an amorphous carbon hardmask 10. The underlying gate conductive layer 8 is patterned using the amorphous carbon hardmask 10 as an etch mask. After patterning, the residual portion of the amorphous carbon hardmask is easily removed by an ashing process in an oxygen or hydrogen atmosphere.
One problem associated with the use of amorphous carbon hardmasks for patterning of polysilicon is delamination of the amorphous carbon from the underlying polysilicon. FIGS. 2a and 2b illustrate this problem. FIG. 2a shows a top view of a patterned amorphous carbon hardmask for patterning a polysilicon gate line. Lattice mismatches between the amorphous carbon and the underlying polysilicon on which it is grown impart compressive forces 14 to the amorphous carbon. As the width of the line decreases relative to its length, the compressive stress along the length of the line become increasingly greater than the stress across the width of the line. So long as there is a layer of material such as an SiON capping layer overlying the amorphous carbon, the compressive stress within the amorphous carbon is restrained. However, when overlying layers are removed or become thin, the internal compressive stress of the amorphous carbon is no longer restrained, and the amorphous carbon delaminates from the underlying polysilicon and may assume a xe2x80x9csquigglexe2x80x9d pattern as shown in FIG. 2b that effectively lengthens the line to relieve the compressive stress. The deformed pattern of the delaminated line will be reproduced in the polysilicon upon further etching, resulting in a deformed gate line.
Consequently, there is a need for methods that avoid the amorphous carbon delamination problem of the conventional method.
Another technique for achieving sub-100 nm gate lines involves trimming of photoresist masks by isotropic etching to reduce photoresist mask feature sizes to below the minimum photoresist feature size achievable through projection lithography. The trimmed photoresist mask is used to pattern an underlying gate conductive layer such as polysilicon, resulting in a gate line that has a width less than the minimum achievable photoresist feature size. However, the resist trim technique is limited by the need to retain a minimum thickness of photoresist in order to accurately transfer the pattern of the photoresist mask to the underlying polysilicon layer. Therefore the trimming process must be terminated before that minimum thickness has been reached. This limits the reductions in gate size that can be achieved by the resist trim technique.
Amorphous carbon hardmasks may also be reduced in size by trimming techniques. However, amorphous carbon hardmasks are also subject to thickness limitations that limit the degree to which they may be trimmed, and are more likely to suffer delamination when trimmed.
Consequently, there is also a need for techniques for reducing gate widths that are not subject to the limitations of the photoresist trim technique.
It is an object of the present invention to improve over the aforementioned conventional methods by reducing the occurrence of gate line deformation and by providing an alternative to the photoresist trim technique for reducing gate line widths.
In accordance with one embodiment of the present invention, a silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon gate conductive layer. The stress relief provided by the silicon oxide stress relief portion reduces the likelihood of delamination of the amorphous carbon from the underlying polysilicon. In a preferred implementation of this embodiment, the silicon oxide stress relief portion is subjected to a selective isotropic etch that trims the width of the silicon oxide, resulting in the formation of a trimmed silicon oxide stress relief portion that has a width that is less than the width of the amorphous carbon hardmask. The trimmed stress relief portion may then be used as an etch mask to pattern the underlying polysilicon.
In another embodiment of the invention, a stress relief portion is provided between a hardmask and a gate conductive layer. The stress relief portion is then subjected to a selective isotropic etch that trims the width of the stress relief portion so that it has a width less than the width of the hardmask. The hardmask may then be removed and the trimmed stress relief portion may be used to pattern the underlying gate conductive layer.